The present invention relates to a field effect semiconductor device comprising a gate electrode and a diffusion layer, and to a process for fabricating the same.
In LSI's such as MPU's of which high speed operation is required, it is necessary to reduce the parasitic resistance by converting the diffusion layer of the field effect semiconductor device into suicides. FIG. 3 shows a process for fabricating a MOS transistor according to a first example previously suggested, in which the diffusion layer is converted into silicide.
In the first example referring to FIG. 3A, an SiO.sub.2 film 12 is formed on the surface of an isolating region of a Si substrate 11 by means of LOCOS process and the like, and another SiO.sub.2 film 13 is formed on the surface of the active region surrounded by the SiO.sub.2 film 12. Then, after forming a gate electrode using the impurity-doped polycrystalline Si film 14, implantation of impurity ions is effected by using the polycrystalline Si film 14 and the SiO.sub.2 film 12 as masks to form a lightly-doped diffusion layer 15.
After forming side walls made of an SiO.sub.2 film 16 or an SiN film and the like on the side of the polycrystalline Si film 14, a diffusion layer 17 containing impurity at a high concentration is formed by means of implantation of impurities ions using the polycrystalline Si film 14 and the SiO.sub.2 films 16 and 12 as masks. Then, Ti film 21 or Co film and the like is deposited over the entire surface.
Referring to FIG. 3B, the Si substrate 11 exposed where not masked by the SiO.sub.2 films 12 and 16 and the polycrystalline Si film 14 are reacted with the Ti film 21 or the like by means of annealing in the temperature range of from 600 to 800.degree. C. to form a TiSi.sub.2 film 22 or a CoSi.sub.2 film and the like. As a result, a titanium polycide layer 23 comprising the polycrystalline Si film 14 and the TiSi.sub.2 film 22 provides the gate electrode. Then the Ti film 21 and the like which remain non-reacted on the SiO.sub.2 films 12 and 16 are removed.
Referring to FIG. 3C, an interlayer, insulating film 24 is formed, and a contact hole 25 which reaches the TiSi.sub.2 film 22 provided on the surface of the diffusion layer 17 is formed in the interlayer insulating film 24. If the contact hole 25 should be misaligned from the TiSi.sub.2 film 22, the contact resistance becomes too high because the bird's beak of the SiO.sub.2 film 12 is etched as shown in FIG. 3C as to expose the portion of the Si substrate 11 having no diffusion layer 17 formed thereon.
Accordingly, an impurity 26 is introduced into the Si substrate 11 by means of contact compensation ion implantation to newly form a diffusion layer 27 (FIG. 3D). Then, referring to FIG. 3D, the contact hole 25 is filled with a tungsten plug 31, an interconnection is formed with an Al film 32, and a passivation film (not shown in the figure) is formed to obtain a complete MOS transistor of an LDD structure.
FIG. 4 shows a fabrication process of the first half of a second example previously suggested. In the process referring to FIG. 4A, a polycrystalline Si film 14, a WSi.sub.x film 33, and an SiO.sub.2 film 34 are processed into a pattern of a gate electrode as to form a gate electrode of a tungsten polycide layer 35 comprising the polycrystalline Si film 14 and the WSi.sub.x film 33. Then, referring to FIG. 4B, substantially the same process steps as those of the first example shown with reference to FIG. 3 are effected, except that the TiSi.sub.2 film 22 is formed only on the surface of the diffusion layer 17.
However, in both of the first and second examples above, the surface portion of the Si substrate 11 itself is converted into a silicide to form the TiSi.sub.2 film 22 on the surface of the diffusion layer 17. This induces high stress that is applied to the Si substrate 11, and particularly, to the Si substrate 11 in the vicinity of the bird's beak of the SiO.sub.2 film. Thus, crystal defects are found apt to form on the Si substrate 11, and in case the diffusion layer 17 is shallow, a junction leak current is likely to generate in the diffusion layer 17.
The junction leak current attributed to crystal defects can be prevented from occurring by deepening the diffusion layer 17 in such a manner that the crystal defects are included in the diffusion layer 17. However, if the diffusion layer 17 should be provided deep, it becomes difficult to suppress the short channel effect to make a fine MOS transistor unfeasible.
Furthermore, in case the diffusion layer 17 is provided deep as is shown in FIG. 5 when a diffusion layer 36 is provided as the so-called pocket layer, the position if the junction of the diffusion layer 17 cannot be determined, but varies in the longitudinal direction of the channel due to the variation in the width of the SiO.sub.2 film 16 provided as the side wall. This leads to the variation in width of the diffusion layer 36. Thus, as is clearly understood from FIG. 5, the shape of the depletion layer 37 also varies to make the threshold voltage undecided.
Furthermore, in CMOS transistors, although contact compensation ion implantation is performed to cope with the case the contact hole 25 is misaligned from the TiSi.sub.2 film as shown in FIG. 3C, an additional lithography step is required to cover the MOS transistor having the opposite conductive type. Accordingly, the number of process steps increases as a whole to elevate the cost of fabrication.
Furthermore, annealing at a temperature of 800.degree. C. or higher is necessary to activate the impurity 26 introduced by contact compensation ion implantation. However, at this process stage, the TiSi.sub.2 film 22 is already formed. Thus, the annealing grows and isolates the crystal grains in the TiSi.sub.2 film as to lead to a problematic increase in the resistance of the TiSi.sub.2 film 22.
To prevent the contact holes 25 from the misalignment with respect to the TiSi.sub.2 film, the distance between the contact hole 25 and the SiO.sub.2 film 12 may be increased by expanding the area of the element active region. But this means is in conflict with the aim of implementing a finer MOS transistor.